HI SPEED USB 2.0 DRIVER SERIAL
HI SPEED USB 2.0 DRIVER DRIVER

Support Microsoft Windows 98SE/ME, 2000, XP, and Vista Д¤8-pin LQFP (Body Size: 7Г—7 mm) 48-pin QFN (Body Size: 6Г—6 mm, 0.

Standard downstream port status indicators (Green and Amber LED control for each downstream port).

Removable or Non-Removable Downstream Devices configuration.

Global or Individual Over-Current Detection Mode select.

Ganged or Individual Power Control Mode select.

Automatic re-enumeration when Self-Powered switching to Bus-Powered.

Automatic self-power status monitoring.

Each TT could handle 64 periodic Start-Split transactions, 32 periodic Complete-Split transactions, and 6 none-periodic transactions.

HI SPEED USB 2.0 DRIVER DRIVER

The in-box driver uses the supplied jack information when handling the KSPROPERTYJACKDESCRIPTION for this device.

Alternate Interface 0 for Single-TT, and Starting in Windows 10 release 1703, IHVs that create USB Audio Class 2.0 devices having one or more jacks have the capability to describe these jacks to the in-box Audio Class 2.0 driver.Integrated 12MHz-to-480MHz Phase Lock Loop (PLL).Integrated 12MHz Oscillator with feedback resister, and crystal load capacitance.Integrated 5V to 3.3V and 1.8V regulator.

HI SPEED USB 2.0 DRIVER SERIAL

Integrated upstream 1.5KО© pull-up, downstream 15KО© pull-down, and serial resisters.

4 downstream facing ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.5MHz) modes.

Upstream facing port supports High-Speed (480MHz) and Full-Speed (12MHz) modes.

Fully compliant with Universal Serial Bus Specification Revision 2.0 (USB 2.0).

64 mA when one Downstream port enabled in High-Speed mode.

115 mA when four Downstream ports enabled in High-Speed mode.

Most part of the chip will not be clocked unless needed. Low power consumption is achieved by using 0.18Ојm technology and comprehensive power/clock control mechanism. Special Build-In-Self-Test mode is designed to exercise all high, full, and low speed analog components on the packaging and testing stage as well. To guarantee high quality, the whole chip is covered by Test Scan Chain вЂ“ include even the high speed (480MHz) modules, so that all the logic components could be fully tested before shipping. The whole design is based on state-machine-control to reduce the response delay time no micro controller is used in this chip. Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming. It adopts Multiple Transaction Translator (MTT) architecture to explore the maximum possible throughput.

Hi speed usb 2.0 driver